Designers of printed circuit boards ("PCBs") for modern digital systems face an ever-present demand for increase component density and trace density. Moreover, as device fabrication technology has advanced, the intended operating speeds for digital components have also steadily increased, resulting in PCB mounting requirements that often conflict with one another. On the one hand, increased operating speeds mean higher heat generation per component, which is a factor that militates for placing components at a larger distance from one another in order to ease the problem of heat dissipation. But on the hand, higher operating speeds also usually result in a speed to place components closer together in order to shorten the lengths of the traces that carry high-speed signals between them.
These problems become particularly troublesome in the context of mounting multiple indentical processors on the same PCB and coupling of each of the processors to a single secondary component such as a bus interface device. First, processor chips are among the highest heat generating devices in a digital system because of their high operating speeds. Second, PCB traces begin to operate like waveguides when carrying high-frequency digital signals; therfore, not only should they be as short as possible, but even their topologies become important design constraints. Third, each integrated circuit package contains internal conductors that connect the die to the external chip pads. When multiple processors are to be connected to a single bus interface device to form high-speed bus, the aggregate length of each conductive path from die to die should be the same, including the lengths of the internal conductors as well as the lenghts of the external PCB traces.
It is therefore an object of the invention to provide a high-speed component PCB mounting arrangement that strikes a uniquely advantageous balance between component proximity, trace length and trace length symmetry.
It is further object of the invention to provide such a uniquely advantageous PCB mounting arrangements for multiple identical processes and a single secondary component such as a bus interface device, wherein the multiple indentical processors and the secondary component must be coupled together to form a high-speed bus.